NXP Semiconductors MPC5566, Reference Manual

Page: 420 / 1268

Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 10-7
Figure 10-6. Hardware Vector Mode: Interrupt Exception Handler Address Calculation
The processor negates INTC’s interrupt request when automatically acknowledging the interrupt request.
However, the interrupt request to the processor do not negate if a higher priority interrupt request arrives.
Even in this case, the interrupt vector number does not update to the higher priority request until the lower
priority request is acknowledged by the processor.
The assertion of the interrupt acknowledge signal pushes the PRI value in the INTC_CPR onto the LIFO
and updates PRI in the INTC_CPR with the new priority.
10.2 External Signal Description
The INTC does not have any direct external MCU signals. However, there are sixteen external pins which
can be configured in the SIU as external interrupt request input pins. When configured for an external
interrupt request function, an interrupt on that pin sets an external interrupt flag. These flags cause one of
five peripheral interrupt requests to the interrupt controller.
For more information on external interrupts, the pins used, and how to configure them:
• Refer to Table 10-2 for a list and number of the external interrupt pins.
• Refer to the SIU chapter for more information on these pins.
Table 10-2. External Interrupt Signals
Function
1
P/A/G
2
Description
I/O
Type
Reset
Function/
State
3
Post Reset
Function/
State
4
EMIOS[14]_ P eMIOS channel O — / WKPCFG — / WKPCFG
IRQ[0]_ A External interrupt request I
CNTXD A CAN D transmit O
GPIO[193] G GPIO I/O
31 16 15 0
IVPR
31 28 27 16 15 0 0
+ Hardware vector
15 0
0b0000 INTC_IACKR[INTVEC]
PREFIX
0x0000
PREFIX
18
0b000
19
0x0000
31 28 27 16
0b0000 IRQ SPECIFIC OFFSET
18
0b000
19 16
= Interrupt exception
handler address
mode offset