NXP Semiconductors MPC5566, Reference Manual

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System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-43
Figure 6-45. TEA_GPIO[71] Pad Configuration Register (SIU_PCR71)
Refer to Table 6-19 for bit field definitions. Table 6-45 lists the PA fields for TEA_GPIO[71].
6.3.1.45 Pad Configuration Register 72 (SIU_PCR72)
The SIU_PCR72 register controls the function, direction, and electrical attributes of
BR_FEC_MDC_GPIO[72]. This register allows selection of the GPIO functions.
Figure 6-46.
To use the BR function, the PA field must be set to BR before EBI_MCR[EXTM] is set.
BR_FEC_MDC_GPIO[72] Pad Configuration Register (SIU_PCR72)
Refer to Table 6-19 for bit field definitions. Table 6-46 lists the PA field for BR_FEC_MDC_GPIO[72].
Address: Base + 0x00CE Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
PA OBE
1
1
When configured as TEA, the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as TEA and external master operation is enabled, clear the ODE bit to 0.
HYS
4
4
When EBI is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as TEA.
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-45. PCR71 PA Field Definition
PA Field Pin Function
0b0 GPIO[71]
0b1 TEA
Address: Base + 0x00D0 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE IBE DSC ODE
1
1
When configured as BR and external master operation is enabled, clear the ODE bit to 0.
HYS
0 0
WPE WPS
5
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Table 6-46. PCR72 PA Field Definition
PA Field Pin Function
0b00 GPIO[72]
0b01 BR
0b10 FEC_MDC
0b11 Invalid value