NXP Semiconductors MPC5566, Reference Manual

Page: 193 / 1268

Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
5-4 Freescale Semiconductor
5.2 External Signal Description
The PBRIDGE has no external signals.
5.3 Memory Map and Register Definitions
The memory map for the 32-bit PBRIDGE A registers is shown in Table 5-2 .
The memory map for the 32-bit PBRIDGE B registers is shown Table 5-3 .
5.3.1 Register Descriptions
There are three types of registers that control each PBRIDGE. All registers are 32-bit registers and must
be accessed in supervisor mode by trusted bus masters. Additionally, these registers must only be read
from or written to by a 32-bit aligned access. PBRIDGE registers are mapped into the PBRIDGE A and
Table 5-2. PBRIDGE A Memory Map
Address Register Name Register Description Bits
Base (0xC3F0_0000) PBRIDGE_A_MPCR Master privilege control register 32
Base + (0x0004–0x001F) — Reserved —
Base + 0x0020 PBRIDGE_A_PACR0 Peripheral access control register 0 32
Base + ( 0x0024–0x003F) — Reserved —
Base + 0x0040 PBRIDGE_A_OPACR0 Off-platform peripheral access control register 0 32
Base + 0x0044 PBRIDGE_A_OPACR1 Off-platform peripheral access control register 1 32
Base + 0x0048 PBRIDGE_A_OPACR2 Off-platform peripheral access control register 2 32
Base + (0x004C–0x0053) — Reserved —
Table 5-3. PBRIDGE B Memory Map
Address Register Name Register Description Bits
Base (0xFFF0_0000) PBRIDGE_B_MPCR Master privilege control register 32
Base + (0x0004–0x001F) — Reserved —
Base + 0x0020 PBRIDGE_B_PACR0 Peripheral access control register 0 32
Base + (0x0024–0x0027) — Reserved —
Base + 0x0028 PBRIDGE_B_PACR2 Peripheral access control register 2 32
Base + (0x002C–0x003F) — Reserved —
Base + 0x0040 PBRIDGE_B_OPACR0 Off-platform peripheral access control register 0 32
Base + 0x0044 PBRIDGE_B_OPACR1 Off-platform peripheral access control register 1 32
Base + 0x0048 PBRIDGE_B_OPACR2 Off-platform peripheral access control register 2 32
Base + 0x004C PBRIDGE_B_OPACR3 Off-platform peripheral access control register 3 32
Base + (0x0050–0x0053) — Reserved —