NXP Semiconductors MPC5566, Reference Manual

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Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25-71
Table 25-42 an example data write message with 12 MDO and two MSEO configuration.
T0, A0, D0 are the least significant bits (LSB) where:
• Tx = TCODE number (fixed)
• Sx = Source processor (fixed)
• Zx = Data size (fixed)
• Ax = Unique portion of the address (variable)
• Dx = Write data (variable: 8-, 16- or 32-bit)
25.14.10 IEEE
®
1149.1 (JTAG) RD/WR Sequences
This section contains example JTAG/OnCE sequences used to access resources.
25.14.10.1 JTAG Sequence for Accessing Internal Nexus Registers
Table 25-41. Direct Branch Message Example (12 MDO and 2 MSEO)
Clock
MDO[11:0]
MSEO[1:0] State
11 10 9 8 7 6 5 4 3 2 1 0
0 X X X X X X X X X X X X 1 1 Idle (or end of last message)
1 I1 I0 S3 S2 S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start Message
2 0 0 0 0 0 0 0 0 0 0 I3 I2 1 1 End Packet and End Message
3 X X X X S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start of Next Message
Table 25-42. Direct Write Message Example (12 MDO and 2 MSEO)
Clock
MDO[11:0]
MSEO[1:0] State
11 10 9 8 7 6 5 4 3 2 1 0
0 X X X X X X X X X X X X 1 1 Idle (or end of last message)
1 Z1 Z0 S3 S2 S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start Message
2 0 0 0 0 0 0 0 A3 A2 A1 A0 Z2 0 1 End Packet
3 X X X X D7 D6 D5 D4 D3 D2 D1 D0 1 1 End Packet/End Message
Table 25-43. Accessing Internal Nexus3 Registers via JTAG/OnCE
Step # TMS Pin Description
1 1 IDLE
−>
SELECT-DR_SCAN
2 0 SELECT-DR_SCAN
−>
CAPTURE-DR (Nexus command register value loaded in shifter)
3 0 CAPTURE-DR
−>
SHIFT-DR
4 0 (7) TCK clocks issued to shift in direction (read/write) bit and first 6 bits of Nexus reg. addr.
5 1 SHIFT-DR
−>
EXIT1-DR (7th bit of Nexus reg. shifted in)