MPC555
/
MPC556
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
22-4
Figure 22-3 TAP Controller State Machine
22.5 Instruction Register
The MPC555 / MPC556 JTAG implementation includes the public instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS), and also supports the CLAMP instruction. One addi-
tional public instruction (HI-Z) provides the capability for disabling all device output driv-
ers. The MPC555 / MPC556 includes a 4-bit instruction register without parity consisting
of a shift register with four parallel outputs. Data is transferred from the shift register to the
parallel outputs during the update-IR controller state. The four bits are used to decode the
five unique instructions listed in
.
TEST LOGIC
RESET
RUN-TEST/IDLE
SELECT-DR_SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT-IR_SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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