MPC555
/
MPC556
CENTRAL PROCESSING UNIT
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
3-26
3.9.10 Implementation-Specific SPRs
The MPC555 / MPC556 includes several implementation-specific SPRs that are not
defined by the PowerPC architecture. These registers can be accessed by supervisor-
level instructions only. These registers are listed in
and
.
3.9.10.1 EIE, EID, and NRI Special-Purpose Registers
The RCPU includes three implementation-specific SPRs to facilitate the software ma-
nipulation of the MSR[RI] and MSR[EE] bits. Issuing the
mtspr
instruction
with one of
these registers as an operand causes the RI and EE bits to be set or cleared as shown
in
A read (
mfspr
) of any of these locations is treated as an unimplemented instruction,
resulting in a software emulation exception.
3.9.10.2 Floating-Point Exception Cause Register (FPECR)
The FPECR is a 32-bit supervisor-level internal status and control register used by the
floating-point assist firmware envelope. It contains four status bits indicating whether
the result of the operation is tiny and whether any of three source operands are denor-
malized. In addition, it contains one control bit to enable or disable SIE mode. This reg-
ister must not be accessed by user code.
Table 3-16 Processor Version Register Bit Descriptions
Bit(s)
Name
Description
0:15
VERSION
A 16-bit number that identifies the version of the processor and of the PowerPC architec-
ture. MPC555 / MPC556 value is 0x0002.
16:31
REVISION
A 16-bit number that distinguishes between various releases of a particular version. The
MPC555 / MPC556 value is 0x0020.
Table 3-17 EIE, EID, AND NRI Registers
SPR Number
(Decimal)
Mnemonic
MSR[EE]
MSR[RI]
80
EIE
1
1
81
EID
0
1
82
NRI
0
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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