NXP Semiconductors MKW01Z128, Reference Manual

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32.2.7 UART Control Register 3 (UARTx_C3)
Address: Base a 6h offset
Bit 7 6 5 4 3 2 1 0
Read
R8T9 R9T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Write
Reset 0 0 0 0 0 0 0 0
UARTx_C3 field descriptions
Field Description
7
R8T9
Receive Bit 8 / Transmit Bit 9
When the UART is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the
left of the msb of the buffered data in the UART_D register. When reading 9-bit data, read R8 before
reading UART_D because reading UART_D completes automatic flag clearing sequences that could allow
R8 and UART_D to be overwritten with new data.
When the UART is configured for 10-bit data (M10 = 1), T9 may be thought of as a tenth transmit data bit.
When writing 10-bit data, the entire 10-bit value is transferred to the UART transmit buffer when UART_D
is written so T9 and T8 should be written, if it needs to change from its previous value, before UART_D is
written. If T9 and T8 do not need to change in the new value, such as when it is used to generate mark or
space parity, they need not be written each time UART_D is written.
6
R9T8
Receive Bit 9 / Transmit Bit 8
When the UART is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to
the left of the msb of the data in the UART_D register. When writing 9-bit data, the entire 9-bit value is
transferred to the UART transmit buffer after UART_D is written so T8 should be written, if it needs to
change from its previous value, before UART_D is written. If T8 does not need to change in the new value,
such as when it is used to generate mark or space parity, it need not be written each time UART_D is
written.
When the UART is configured for 10-bit data (M10 = 1), R9 can be thought of as a tenth receive data bit.
When reading 10-bit data, read R9 and R8 before reading UART_D because reading UART_D completes
automatic flag clearing sequences that could allow R8, R9 and UART_D to be overwritten with new data.
5
TXDIR
UART_TX Pin Direction in Single-Wire Mode
When the UART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit
determines the direction of data at the UART_TXD pin. When clearing TXDIR, the transmitter will finish
receiving the current character (if any) before the receiver starts receiving data from the UART_TXD pin.
0 UART_TXD pin is an input in single-wire mode.
1 UART_TXD pin is an output in single-wire mode.
4
TXINV
Transmit Data Inversion
Setting this bit reverses the polarity of the transmitted data output.
NOTE: Setting TXINV inverts the UART_TXD output for all cases: data bits, start and stop bits, break,
and idle.
0 Transmit data not inverted.
1 Transmit data inverted.
3
ORIE
Overrun Interrupt Enable
This bit enables the overrun flag (OR) to generate hardware interrupt requests.
Table continues on the next page...
Chapter 32 Universal asynchronous receiver/transmitter (UART0)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 631