NXP Semiconductors MKW01Z128, Reference Manual

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31.3.3 SPI Control Register 2 (SPIx_C2)
This read/write register is used to control optional features of the SPI system.
Address: Base a 2h offset
Bit 7 6 5 4 3 2 1 0
Read
SPMIE SPIMODE TXDMAE MODFEN BIDIROE RXDMAE SPISWAI SPC0
Write
Reset 0 0 0 0 0 0 0 0
SPIx_C2 field descriptions
Field Description
7
SPMIE
SPI Match Interrupt Enable
This is the interrupt enable bit for the SPI receive data buffer hardware match (SPMF) function.
0 Interrupts from SPMF inhibited (use polling)
1 When SPMF is 1, requests a hardware interrupt
6
SPIMODE
SPI 8-bit or 16-bit mode
This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length. In master mode, a
change of this bit aborts a transmission in progress, forces the SPI system into an idle state, and resets all
status bits in the S register. Refer to the description of “Data Transmission Length” for details.
0 8-bit SPI shift register, match register, and buffers
1 16-bit SPI shift register, match register, and buffers
5
TXDMAE
Transmit DMA enable
This bit enables a transmit DMA request. When this bit is set to 1, a transmit DMA request is asserted
when both SPTEF and SPE are set, and the interrupt from SPTEF is disabled.
0 DMA request for transmit is disabled and interrupt from SPTEF is allowed
1 DMA request for transmit is enabled and interrupt from SPTEF is disabled
4
MODFEN
Master Mode-Fault Function Enable
When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave
select input.) In master mode, this bit determines how the SS pin is used. For details, refer to the
description of the SSOE bit in the C1 register.
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
3
BIDIROE
Bidirectional Mode Output Enable
When bidirectional mode is enabled because SPI pin control 0 (SPC0) is set to 1, BIDIROE determines
whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether
the SPI is configured as a master or a slave, it uses the MOSI (MOMI) or MISO (SISO) pin, respectively,
as the single SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
Table continues on the next page...
Memory map/register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
588 Freescale Semiconductor, Inc.