NXP Semiconductors MKW01Z128, Reference Manual

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31.3.2 SPI Baud Rate Register (SPIx_BR)
Use this register to set the prescaler and bit rate divisor for an SPI master. This register
may be read or written at any time.
Address: Base a 1h offset
Bit 7 6 5 4 3 2 1 0
Read 0
SPPR[2:0] SPR[3:0]
Write
Reset 0 0 0 0 0 0 0 0
SPIx_BR field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–4
SPPR[2:0]
SPI Baud Rate Prescale Divisor
This 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler is
the SPI module clock. The output of this prescaler drives the input of the SPI baud rate divider. Refer to
the description of “SPI Baud Rate Generation” for details.
000 Baud rate prescaler divisor is 1.
001 Baud rate prescaler divisor is 2.
010 Baud rate prescaler divisor is 3.
011 Baud rate prescaler divisor is 4.
100 Baud rate prescaler divisor is 5.
101 Baud rate prescaler divisor is 6.
110 Baud rate prescaler divisor is 7.
111 Baud rate prescaler divisor is 8.
SPR[3:0] SPI Baud Rate Divisor
This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes
from the SPI baud rate prescaler. Refer to the description of “SPI Baud Rate Generation” for details.
0000 Baud rate divisor is 2.
0001 Baud rate divisor is 4.
0010 Baud rate divisor is 8.
0011 Baud rate divisor is 16.
0100 Baud rate divisor is 32.
0101 Baud rate divisor is 64.
0110 Baud rate divisor is 128.
0111 Baud rate divisor is 256.
1000 Baud rate divisor is 512.
All others Reserved
Chapter 31 Serial Peripheral Interface (SPI)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 587