20.3.5 MCG Control 5 Register (MCG_C5)
Address: 4006_4000h base + 4h offset = 4006_4004h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
MCG_C5 field descriptions
Field
Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
PLLCLKEN0
PLL Clock Enable
Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV 0
needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz
range prior to setting the PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, and the external
oscillator is being used as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set.
0
MCGPLLCLK is inactive.
1
MCGPLLCLK is active.
5
PLLSTEN0
PLL Stop Enable
Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if
PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock
to run if it is written to 1.
0
MCGPLLCLK is disabled in any of the Stop modes.
1
MCGPLLCLK is enabled if system is in Normal Stop mode.
PRDIV0
PLL External Reference Divider
Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must
be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the
PRDIV 0 value must not be changed when LOCK0 is zero.
Table 20-1. PLL External Reference Divide Factor
PRDIV
0
Divide
Factor
PRDIV
0
Divide
Factor
PRDIV
0
Divide
Factor
PRDIV
0
Divide
Factor
00000
1
01000
9
10000
17
11000
25
00001
2
01001
10
10001
18
11001
Reserve
d
00010
3
01010
11
10010
19
11010
Reserve
d
00011
4
01011
12
10011
20
11011
Reserve
d
Table continues on the next page...
Chapter 20 Multipurpose Clock Generator (MCG)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc.
343
Summary of Contents for MKW01Z128
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Page 233: ...Module clocks MKW01Z128 MCU Reference Manual Rev 3 04 2016 102 Freescale Semiconductor Inc...
Page 513: ...Interrupts MKW01Z128 MCU Reference Manual Rev 3 04 2016 382 Freescale Semiconductor Inc...
Page 633: ...CMP Trigger Mode MKW01Z128 MCU Reference Manual Rev 3 04 2016 502 Freescale Semiconductor Inc...