NXP Semiconductors MKW01Z128, Reference Manual

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MCG_C4 field descriptions
Field Description
7
DMX32
DCO Maximum Frequency with 32.768 kHz Reference
The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a
32.768 kHz reference.
The following table identifies settings for the DCO frequency range.
NOTE: The system clocks derived from this source should not exceed their specified maximums.
DRST_DRS DMX32 Reference Range FLL Factor DCO Range
00 0 31.25–39.0625 kHz 640 20–25 MHz
1 32.768 kHz 732 24 MHz
01 0 31.25–39.0625 kHz 1280 40–50 MHz
1 32.768 kHz 1464 48 MHz
10 0 31.25–39.0625 kHz 1920 60–75 MHz
1 32.768 kHz 2197 72 MHz
11 0 31.25–39.0625 kHz 2560 80–100 MHz
1 32.768 kHz 2929 96 MHz
0 DCO has a default range of 25%.
1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
6–5
DRST_DRS
DCO Range Select
The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to
the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The
DRST field does not update immediately after a write to the DRS field due to internal synchronization
between clock domains. See the DCO Frequency Range table for more details.
00 Encoding 0 — Low range (reset default).
01 Encoding 1 — Mid range.
10 Encoding 2 — Mid-high range.
11 Encoding 3 — High range.
4–1
FCTRIM
Fast Internal Reference Clock Trim Setting
FCTRIM
1
controls the fast internal reference clock frequency by controlling the fast internal reference
clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing
the binary value increases the period, and decreasing the value decreases the period.
If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that
value from the nonvolatile memory location to this register.
0
SCFTRIM
Slow Internal Reference Clock Fine Trim
SCFTRIM
2
controls the smallest adjustment of the slow internal reference clock frequency. Setting
SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount
possible.
If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value
from the nonvolatile memory location to this bit.
1. A value for FCTRIM is loaded during reset from a factory programmed location.
2. A value for SCFTRIM is loaded during reset from a factory programmed location.
Memory Map/Register Definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
342 Freescale Semiconductor, Inc.