NXP Semiconductors MKW01Z128, Reference Manual

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AIPS_MPRA field descriptions (continued)
Field Description
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
21
MTW2
Master 2 Trusted For Writes
Determines whether the master is trusted for write accesses.
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
20
MPL2
Master 2 Privilege Level
Specifies how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.
19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18
MTR3
Master 3 Trusted For Read
Determines whether the master is trusted for read accesses.
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
17
MTW3
Master 3 Trusted For Writes
Determines whether the master is trusted for write accesses.
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
16
MPL3
Master 3 Privilege Level
Specifies how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.
17.2.2 Peripheral Access Control Register (AIPS_PACRn)
Each PACR register consists of eight 4-bit PACR fields. Each PACR field defines the
access levels for a particular peripheral. The mapping between a peripheral and its PACR
field is shown in the table below. The peripheral assignment to each PACR is defined by
the memory map slot that the peripheral is assigned to. See this chip's memory map for
the assignment of a particular peripheral.
The following table shows the location of each peripheral slot's PACR field in the PACR
registers.
Memory map/register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
294 Freescale Semiconductor, Inc.