NXP Semiconductors MKW01Z128, Reference Manual, Page: 241 / 884

• DWT
• NVIC
• Crossbar bus switch
• AHB-AP
1
• Private peripheral bus
1
4.3 Boot
The information found here describes the boot sequence, including sources and options.
Some configuration information such as clock trim values stored in factory programmed
flash locations is autoloaded.
4.3.1 Boot sources
The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR)
to relocate the exception vector table. This device supports booting from internal flash
and RAM.
This device supports booting from internal flash with the reset vectors located at
addresses 0x0 (initial SP_main), 0x4 (initial PC), and RAM with relocating the exception
vector table to RAM.
4.3.2 FOPT boot options
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains read-
only bits that are loaded from the NVM's option byte in the flash configuration field. The
default setting for all values in the FTFA_FOPT register is logic 1 since it is copied from
the option byte residing in flash, which has all bits as logic 1 in the flash erased state. To
configure for alternate settings, program the appropriate bits in the NVM option byte.
The new settings will take effect on subsequent POR, VLLSx recoveries, and any system
reset. For more details on programming the option byte, see the flash memory chapter.
1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available
during System Reset.
Boot
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
110 Freescale Semiconductor, Inc.