NXP Semiconductors MKW01Z128, Reference Manual, Page: 210 / 884

Table 1-48. Ports summary (continued)
Feature Port A Port B Port C Port D Port E
Interrupt and DMA
request
Yes No Yes Yes No
Digital glitch filter No No No No No
1. UART signals can be configured for open-drain using SIM_SOPT5 register. IIC signals are automatically enabled for open
drain when selected.
1.10.1.3 GPIO accessibility in the memory map
The GPIO is multi-ported and can be accessed directly by the core with zero wait states at
base address 0xF800_0000. It can also be accessed by the core and DMA masters
through the cross bar/AIPS interface at 0x400F_F000 and at an aliased slot (15) at
address 0x4000_F000. All BME operations to the GPIO space can be accomplished
referencing the aliased slot (15) at address 0x4000_F000. Only some of the BME
operations can be accomplished referencing GPIO at address 0x400F_F000.
1.10.2 TSI configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal m
ultiple
xing
Register
access
Peripheral
bridge
Module signals
Touch sense input
module
Figure 1-33. TSI configuration
Table 1-49. Reference links to related information
Topic Related module Reference
Full description TSI TSI
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
Chapter 1 Chip Configuration
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 79