NXP Semiconductors MKW01Z128, Reference Manual, Page: 180 / 884

1.4.8.2 DMA transfers via PIT trigger
The PIT module can trigger a DMA transfer on the first two DMA channels. The
assignments are detailed at
PIT/DMA periodic trigger assignments .
1.4.9 DMA Controller Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
DMA Controller
Cr
ossbar s
witch
Requests
Peripheral
bridge 0
Register
access
Transfers
DMA Multiple
xer
Figure 1-12. DMA Controller configuration
Table 1-21. Reference links to related information
Topic Related module Reference
Full description DMA controller DMA controller
System memory map System memory map
Clocking Clock distribution
Power management Power management
Crossbar switch Crossbar switch Crossbar switch
Requests DMA request sources
1.4.10 Computer operating properly (COP) watchdog
configuration
This section summarizes how the module has been configured in the chip.
Chapter 1 Chip Configuration
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 49