NXP Semiconductors MKL27Z128VFM4, Reference Manual

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40.4.2 SAI Transmit Configuration 2 Register (I2Sx_TCR2)
This register must not be altered when TCSR[TE] is set.
Address: 4002_F000h base + 8h offset = 4002_F008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SYNC BCS BCI MSEL BCP BCD
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DIV
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_TCR2 field descriptions
Field Description
31–30
SYNC Synchronous Mode
Configures between asynchronous and synchronous modes of operation. When configured for a
synchronous mode of operation, the receiver must be configured for asynchronous operation.
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.
29
BCS
Bit Clock Swap
This field swaps the bit clock used by the transmitter. When the transmitter is configured in asynchronous
mode and this bit is set, the transmitter is clocked by the receiver bit clock (SAI_RX_BCLK). This allows
the transmitter and receiver to share the same bit clock, but the transmitter continues to use the transmit
frame sync (SAI_TX_SYNC).
When the transmitter is configured in synchronous mode, the transmitter BCS field and receiver BCS field
must be set to the same value. When both are set, the transmitter and receiver are both clocked by the
transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync (SAI_RX_SYNC).
0 Use the normal bit clock source.
1 Swap the bit clock source.
28
BCI
Bit Clock Input
When this field is set and using an internally generated bit clock in either synchronous or asynchronous
mode, the bit clock actually used by the transmitter is delayed by the pad output delay (the transmitter is
clocked by the pad input as if the clock was externally generated). This has the effect of decreasing the
data input setup time, but increasing the data output valid time.
The slave mode timing from the datasheet should be used for the transmitter when this bit is set. In
synchronous mode, this bit allows the transmitter to use the slave mode timing from the datasheet, while
the receiver uses the master mode timing. This field has no effect when configured for an externally
generated bit clock .
0 No effect.
1 Internal logic is clocked as if bit clock was externally generated.
Table continues on the next page...
Chapter 40 Synchronous Audio Interface (SAI)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc. 795