NXP Semiconductors MKL27Z128VFM4, Reference Manual

Page: 682 / 939

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_C03E
UART 7816 Wait and Guard Parameter Register
(UART2_WGP7816_T1)
8 R/W 06h
38.4.27/
707
4006_C03F
UART 7816 Wait Parameter Register C
(UART2_WP7816C_T1)
8 R/W 0Bh
38.4.28/
707
38.4.1 UART Baud Rate Registers: High (UARTx_BDH)
This register, along with the BDL register, controls the prescale divisor for UART baud
rate generation. To update the 13-bit baud rate setting (SBR[12:0]), first write to BDH to
buffer the high half of the new value and then write to BDL. The working value in BDH
does not change until BDL is written.
BDL is reset to a nonzero value, but after reset, the baud rate generator remains disabled
until the first time the receiver or transmitter is enabled, that is, when C2[RE] or C2[TE]
is set.
Address: 4006_C000h base + 0h offset = 4006_C000h
Bit 7 6 5 4 3 2 1 0
Read
Reserved RXEDGIE
0
SBR
Write
Reset 0 0 0 0 0 0 0 0
UARTx_BDH field descriptions
Field Description
7
Reserved
Reserved.
This field is reserved.
6
RXEDGIE
RxD Input Active Edge Interrupt Enable
Enables the receive input active edge, RXEDGIF, to generate interrupt requests.
0 Hardware interrupts from RXEDGIF disabled using polling.
1 RXEDGIF interrupt request enabled.
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
SBR UART Baud Rate Bits
The baud rate for the UART is determined by the 13 SBR fields. See Baud rate generation for details.
NOTE:
• The baud rate generator is disabled until C2[TE] or C2[RE] is set for the first time after
reset.The baud rate generator is disabled when SBR = 0.
• Writing to BDH has no effect without writing to BDL, because writing to BDH puts the data
in a temporary location until BDL is written.
Memory map and registers
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
682 Freescale Semiconductor, Inc.