write is ignored. When the transmit DMA request is enabled (TXDMAE is 1) when
S[SPTEF] is set, the SPI data registers can be written automatically by DMA without
reading the S register first.
Data may be read from the SPI data registers any time after S[SPRF] is set and before
another transfer is finished. Failure to read the data out of the receive data buffer before a
new transfer ends causes a receive overrun condition, and the data from the new transfer
is lost. The new data is lost because the receive buffer still held the previous character
and was not ready to accept the new data. There is no indication for a receive overrun
condition, so the application system designer must ensure that previous data has been
read from the receive buffer before a new transfer is initiated.
In 8-bit mode, only the DL register is available. Reads of the DH register return all zeros.
Writes to the DH register are ignored.
In 16-bit mode, reading either byte (the DH or DL register) latches the contents of both
bytes into a buffer where they remain latched until the other byte is read. Writing to
either byte (the DH or DL register) latches the value into a buffer. When both bytes have
been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
Address: Base a 6h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
SPIx_DL field descriptions
Field
Description
Bits[7:0]
Data (low byte)
35.4.8 SPI data register high (SPIx_DH)
Refer to the description of the DL register.
Address: Base a 7h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
SPIx_DH field descriptions
Field
Description
Bits[15:8]
Data (high byte)
Memory map/register definition
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
584
Freescale Semiconductor, Inc.
