In 16-bit mode, reading either byte (the MH or ML register) latches the contents of both
bytes into a buffer where they remain latched until the other byte is read. Writing to
either byte (the MH or ML register) latches the value into a buffer. When both bytes have
been written, they are transferred as a coherent value into the SPI match registers.
Address: Base a 4h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
SPIx_ML field descriptions
Field
Description
Bits[7:0]
Hardware compare value (low byte)
35.4.6 SPI match register high (SPIx_MH)
Refer to the description of the ML register.
Address: Base a 5h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
SPIx_MH field descriptions
Field
Description
Bits[15:8]
Hardware compare value (high byte)
35.4.7 SPI Data Register low (SPIx_DL)
This register, together with the DH register, is both the input and output register for SPI
data. A write to the registers writes to the transmit data buffer, allowing data to be queued
and transmitted.
When the SPI is configured as a master, data queued in the transmit data buffer is
transmitted immediately after the previous transmission has completed.
The SPTEF bit in the S register indicates when the transmit data buffer is ready to accept
new data. When the transmit DMA request is disabled (TXDMAE is 0): The S register
must be read when S[SPTEF] is set before writing to the SPI data registers; otherwise, the
Chapter 35 Serial Peripheral Interface (SPI)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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