NXP Semiconductors MKL27Z128VFM4, Reference Manual

Page: 158 / 939

12.3.9 System Clock Gating Control Register 5 (SIM_SCGC5)
Address: 4004_7000h base + 1038h offset = 4004_8038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
FLEXIO
0
LPUART1 LPUART0
0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PORTE PORTD PORTC PORTB PORTA
1 0 0 0 1
LPTMR
W
Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0
SIM_SCGC5 field descriptions
Field Description
31
FLEXIO
FlexIO Module
This bit controls the clock gate to the FlexIO Module.
0 Clock disabled
1 Clock enabled
30–22
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21
LPUART1
LPUART1 Clock Gate Control
This bit controls the clock gate to the LPUART1 module.
0 Clock disabled
1 Clock enabled
20
LPUART0
LPUART0 Clock Gate Control
This bit controls the clock gate to the LPUART0 module.
0 Clock disabled
1 Clock enabled
19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
PORTE
Port E Clock Gate Control
Controls the clock gate to the Port E module.
Table continues on the next page...
Memory map and register definition
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
158 Freescale Semiconductor, Inc.