Table 8. Serial downloader I/Os table
Signals
Recommendation
Description
1.UART1
The serial downloader provides a means to download a
program image to the chip over the USB and UART serial
connections. In this mode, the ROM programs the WDOG1
for a time-out specified by the fuse WDOG time-out select
(see the Fusemap chapter for details) if the WDOG_ENABLE
eFuse is 1 and continuously polls for the USB and UART
connection. If no activity is found on the USB OTG1 and
UART1 and the watchdog timer expires, the Arm core is reset.
The ROM polls for the UART1 and USB1
activity circularly until the ROM gets 0x5A,
0xA6 from the UART RXD or first HID
report from the USB bus. When an active
connection port is found, the ROM uses it
for the PC downloading.
2. USB1
6 Boot, reset, and miscellaneous
See
for the boot, reset, and miscellaneous configurations, such as ON/OFF, TEST_MODE, NC pins, and other.
Table 9. Boot configuration
Item
Recommendation
Description
1. BOOT_CFG[11:0]
The BOOT_CFG signals are required
for a proper functionality and operation
and shall not be left floating during
development if BOOT_CFG fuses and
BT_FUSE_SEL are not configured.
See the “System Boot” chapter in
your chip reference manual for the
correct boot configuration. Note that
an incorrect setting may result in an
improper boot sequence.
2. BOOT_MODE[1:0]
For logic 0:
• Tie to GND through 100K
external resistor
For logic 1:
• Tie to the NVCC_LPSR power domain
through a 4.7K external resistor
BOOT_MODE1 and BOOT_MODE0
each have on-chip pull-down devices
with a nominal value of 35 kΩ. When
the on-chip fuses determine the boot
configuration, both boot mode inputs can
be disconnected.
3. BOOT_CFG and BOOT_MODE
signals multiplexed with RGMII signals
As the BOOT_CFG pins are multiplexed
with RGMII signals, recommend to
add 22K isolation resistors to avoid
malfunction. For BOOT_MODE pins,
suggest to add 4.7K isolation resistors.
Please refer to the EVK design for
reference and try to avoid signal stubs
in layout.
NXP Semiconductors
Boot, reset, and miscellaneous
Hardware Development Guide for the MIMXRT1160/1170 Processor , Rev. 2, 09/2021
User Guide
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