Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
24-153
and
Section 24.6.3.3, “USB Interrupt Enable Register (USBINTR),”
for more
information.
24.12.5 Embedded Design
This is an Embedded USB Host Controller as defined by the EHCI specification and thus does not
implement the PCI configuration registers.
24.12.5.1 Frame Adjust Register
Given that the optional PCI configuration registers are not included in this implementation, there is no
corresponding bit level timing adjustments like those provided by the Frame Adjust register in the PCI
configuration registers. Starts of microframes are timed precisely to 125 µsec using the transceiver clock
as a reference clock. That is, 60 MHz transceiver clock for 8-bit physical interfaces and full-speed serial
interfaces or 30 MHz transceiver clock for 16-bit physical interfaces.
24.12.6 Miscellaneous Variations from EHCI
24.12.6.1 Programmable Physical Interface Behavior
The modules support multiple physical interfaces which can operate in different modes when the module
is configured with the software programmable Physical Interface Modes. The control bits for selecting the
PHY operating mode have been added to the PORTSC
n
register providing a capability that is not defined
by the EHCI specification.
24.12.6.2 Discovery
24.12.6.2.1
Port Reset
The port connect methods specified by EHCI require setting the port reset bit in the register for a duration
of 10 msec. Due to the complexity required to support the attachment of devices that are not high speed
there are counter already present in the design that can count the 10 msec reset pulse to alleviate the
requirement of the software to measure this duration. Therefore, the basic connection is then summarized
as the following:
•
[Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device
has attached.
•
The software shall write a ‘1’ to the reset the device.
•
The software shall write a ‘0’ to the reset the device after 10 msec.
— This step, which is necessary in a standard EHCI design, may be omitted with this
implementation. Should the EHCI host controller driver attempt to write a ‘0’ to the reset bit
while a reset is in progress the write will simple be ignored and the reset will continue until
completion.
•
[Port Change Interrupt] Port enable change occurs to notify the host controller that the device in
now operational and at this point the port speed has been determined.
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...