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Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
24-143
24.11.4.2 Operational Model For Setup Transfers
Section 24.11.3.5, “Control Endpoint Operation Model,”
setup transfer requires special
treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from a
setup packet in an 8-byte buffer within the dQH.
Upon receiving notification of the setup packet, the DCD should handle the setup transfer as demonstrated
here:
1. Copy setup buffer contents from dQH—RX to the software buffer.
2. Acknowledge setup backup by writing a 1 to the corresponding bit in ENDPTSETUPSTAT.
NOTE
The acknowledge must occur before continuing to process the setup packet.
NOTE
After the acknowledge has occurred, the DCD must not attempt to access
the setup buffer in the dQH—RX. Only the local software copy should be
examined.
3. Check for pending data or status dTD's from previous control transfers and flush if any exist as
Section 24.11.5.5, “Flushing/De-Priming an Endpoint
.
”
NOTE
It is possible for the device controller to receive setup packets before
previous control transfers complete. Existing control packets in progress
must be flushed and the new control packet completed.
4. Decode setup packet and prepare data phase [optional] and status phase transfer as required by the
USB Chapter 9 or application specific protocol.
24.11.5 Managing Transfers with Transfer Descriptors
24.11.5.1 Software Link Pointers
It is necessary for the DCD software to maintain head and tail pointers to the for the linked list of dTDs
for each respective queue head. This is necessary because the dQH only maintains pointers to the current
working dTD and the next dTD to be executed. The operations described in next section for managing dTD
will assume the DCD can use reference the head and tail of the dTD linked list.
NOTE
To conserve memory, the reserved fields at the end of the dQH can be used
to store the Head and Tail pointers but it still remains the responsibility of
the DCD to maintain the pointers.
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...