NXP Semiconductors MCF5253, Reference Manual, Page: 317 / 648

Audio Interface Module (AIM)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 17-19
Figure 17-11 illustrates the valid bits in the CDTEXTCONTROL Register and Table 17-9 provides the
description of the bit fields.
Address MBAR2 + 0x88 (U channel 1)
MBAR2 + 0xD8 (U channel 2)
MBAR2 + 0x8C (Q channel 1)
MBAR2 + 0xDC (Q channel 2)
Access: User read only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R UChannel Receive 1 and 2
QChannel Receive 1 and 2
W
Reset – – – – – – – – – – – – – – – –
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R UChannel Receive 1 and 2
QChannel Receive 1 and 2
W
Reset – – – – – – – – – – – – – – – –
Figure 17-10. U Channel Receive and Q Channel Receive Registers
Table 17-8. U Channel Receive and Q Channel Receive Registers Field Descriptions
Field Description
31–0
UCHANNEL RECEIVE 1 AND 2
U channel receive register. Contains next 4 U channel bytes.
31–0
QCHANNEL RECEIVE 1 AND 2
Q channel receive register. Contains next 4 Q channel bytes.
Address MBAR2 + 0x92 Access: User read/write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PRESETEN PRESETCOUNT(6:0)
USYNCMODE
EBU2
USYNCMODE
EBU1
UCHANTXTIM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-11. CDTEXTCONTROL Register
Table 17-9. CDTEXTCONTROL Register Field Descriptions
Field Description Notes
15
PRESETEN
0 No action on free-running sync position counter
1 Preset free-running sync position counter 2, 3
14–8
PRESETCOUNT
Sync presetting count 1, 3