NXP Semiconductors MC9S12XS128, Reference Manual

Page: 334 / 739

Freescale’s Scalable Controller Area Network (S12MSCANV3)
S12XS Family Reference Manual, Rev. 1.13
334 Freescale Semiconductor
generates a receive interrupt
1
(see Section 11.4.7.3, “Receive Interrupt ”) to the CPU. The user’s receive
handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the
interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS
field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid
message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be
over-written by the next message. The buffer will then not be shifted into the FIFO.
When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the
background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt,
or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see
Section 11.3.2.2, “MSCAN Control Register 1 (CANCTL1) ”) where the MSCAN treats its own messages
exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event
that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver.
An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly
received messages with accepted identifiers and another message is correctly received from the CAN bus
with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication
is generated if enabled (see
Section 11.4.7.5, “Error Interrupt ”). The MSCAN remains able to transmit
messages while the receiver FIFO is being filled, but all incoming messages are discarded. As soon as a
receive buffer in the FIFO is available again, new valid messages will be accepted.
11.4.3 Identifier Acceptance Filter
The MSCAN identifier acceptance registers (see Section 11.3.2.12, “MSCAN Identifier Acceptance
Control Register (CANIDAC) ”) define the acceptable patterns of the standard or extended identifier
(ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identifier mask
registers (see
Section 11.3.2.18, “MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) ”).
A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and three bits
in the CANIDAC register (see
Section 11.3.2.12, “MSCAN Identifier Acceptance Control Register
(CANIDAC) ”). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the
acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. If
more than one hit occurs (two or more filters match), the lower hit has priority.
A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU
interrupt loading. The filter is programmable to operate in four different modes:
• Two identifier acceptance filters, each to be applied to:
— The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame:
– Remote transmission request (RTR)
– Identifier extension (IDE)
– Substitute remote request (SRR)
— The 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages.
This mode implements two filters for a full length CAN 2.0B compliant extended identifier.
Although this mode can be used for standard identifiers, it is recommended to use the four or
eight identifier acceptance filters.
1. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.