NXP Semiconductors MC9S12VRP64, Owner Reference Manual

Page: 350 / 555

Timer Module (TIM16B2CV3)
MC9S12VRP Family Reference Manual Rev. 1.3
350 NXP Semiconductors
Read: Anytime
Write: Anytime.
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
11.3.2.10 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will
not affect current status of the bit.
Table 11-11. TSCR2 Field Descriptions
Field Description
7
TOI
Timer Overflow Interrupt Enable
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
2:0
PR[2:0]
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 11-12 .
Table 11-12. Timer Clock Selection
PR2 PR1 PR0 Timer Clock
0 0 0 Bus Clock / 1
0 0 1 Bus Clock / 2
0 1 0 Bus Clock / 4
0 1 1 Bus Clock / 8
1 0 0 Bus Clock / 16
1 0 1 Bus Clock / 32
1 1 0 Bus Clock / 64
1 1 1 Bus Clock / 128
7 6 5 4 3 2 1 0
R
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED C1F C0F
W
Reset 0 0 0 0 0 0 0 0
Figure 11-16. Main Timer Interrupt Flag 1 (TFLG1)