NXP Semiconductors MC9S08PA4, Reference Manual

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14.4.5.2 Fast data tolerance
Figure 14-5 shows how much a fast received frame can be misaligned. The fast stop bit
ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
IDLE OR NEXT FRAME
R
T1
R
T2
R
T3
R
T4
R
T5
R
T6
R
T7
R
T8
R
T9
R
T1
0
R
T1
1
R
T1
2
R
T1
3
R
T1
4
R
T1
5
R
T1
6
DATA
SAMPLES
RECEIVER
RT CLOCK
STOP
Figure 14-5. Fast data
For an 8-bit data and 1 stop bit character, data sampling of the stop bit takes the receiver
9 bit times x 16 RT 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 14-5 , the receiver counts 154 RT cycles at
the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160
RT cycles.
The maximum percent difference between the receiver count and the transmitter count of
a fast 8-bit and 1 stop bit character with no errors is:
((154 - 160) / 154) x 100 = 3.90%
For a 9-bit data or 2 stop bits character, data sampling of the stop bit takes the receiver 10
bit times x 16 RT 10 RT cycles = 170 RT cycles.
With the misaligned character shown in, the receiver counts 170 RT cycles at the point
when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of
a fast 9-bit or 2 stop bits character with no errors is:
((170 - 176) / 170) x 100 = 3.53%
For a 9-bit data and 2 stop bits character, data sampling of the stop bit takes the receiver
11 bit times x 16 RT 10 RT cycles = 186 RT cycles.
With the misaligned character shown in, the receiver counts 186 RT cycles at the point
when the count of the transmitting device is 12 bit times x 16 RT cycles = 192 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of
a fast 9-bit and 2 stop bits character with no errors is:
((186 - 192) / 186) x 100 = 3.23%
Chapter 14 Serial communications interface (SCI)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
NXP Semiconductors 291