NXP Semiconductors MC9S08PA4, Reference Manual

Page: 249 / 401

When a selected edge occurs on the channel input, the current value of the FTM counter
is captured into the CnVH:L registers. At the same time, the CHnF bit is set and the
channel interrupt is generated if enabled by CHnIE = 1. See the following figure.
When a channel is configured for input capture, the CHn pin is an edge-sensitive input.
ELSnB:ELSnA control bits determine which edge, falling or rising, triggers input-capture
event. Note that the maximum frequency for the channel input signal to be detected
correctly is system clock divided by four, which is required to meet Nyquist criteria for
signal sampling.
When either half of the 16-bit capture register (CnVH:L) is read, the other half is latched
into a buffer to support coherent 16-bit access in big-endian or little-endian order. This
read coherency mechanism can be manually reset by writing to CnSC register.
Writes to the CnVH:L registers are ignored in input capture mode.
While in BDM, the input capture function works as configured. When a selected edge
event occurs, the FTM counter value, which is frozen because of BDM, is captured into
the CnVH:L registers and the CHnF bit is set.
channel (n) input
synchronizer
edge
detector
was falling
edge selected?
was rising
edge selected?
rising edge
falling edge
0
1
1
0
0 0
CnVH:L[15:0]
FTM counter
D Q
CLK
D Q
CLK
system clock
channel (n) interrupt
CHnIE
CHnF
Figure 12-7. Input capture mode
The input signal is always delayed three rising edges of the system clock; that is, two
rising edges to the synchronizer plus one more rising edge to the edge detector. In other
words, the CHnF bit is set on the third rising edge of the system clock after a valid edge
occurs on the channel input.
12.4.5 Output compare mode
The output compare mode is selected when (CPWMS = 0) and (MSnB:MSnA = 0:1).
Chapter 12 FlexTimer Module (FTM)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
NXP Semiconductors 249