NXP Semiconductors MC9S08LG16, Reference Manual

Page: 46 / 373

Chapter 3 Modes of Operation
MC9S08LG32 MCU Series, Rev. 5
46 Freescale Semiconductor
Figure 3-1. Allowable Power Mode Transitions for the MC9S08LG32 Series
Figure 3-1 illustrates mode state transitions allowed between the legal states shown in Table 3-1 .
Table 3-3 defines triggers for the various state transitions shown in Figure 3-1 .
Stop2—(Assumes STOPE
bit is set and STOP
instruction executed.) If BDM
or LVD is enabled, stop3 is
invoked rather than stop2.
0 0 x 1 OSCOUT optionally on.
2,3
off partial
powerdown
1 0
1
ENBDM is located in the BDC status and control register (BDCSCR) which is write-accessible only through BDC
commands.
2
Configured within the ICS module based on the settings of IREFSTEN, EREFSTEN, IRCLKEN and ERCLKEN.
3
In stop2, the CPU, flash, ICS and all peripheral modules are powered down except for the RTC and LCD.
Table 3-3. Triggers for Transitions Shown in Figure 3-1 .
Transition # From To Trigger
1 Run Wait WAIT instruction
Wait Run Interrupt or reset
2 Run Stop3 Pre-configure settings shown in Table 3-1 , issue
STOP instruction
Stop3 Run Interrupt or reset
Table 3-2. Power Mode Selections (continued)
Mode of Operation
BDCSCR
BDM
SPMSC1
PMC
SPMSC2
PMC
CPU & Periph CLKs
Affects on
Sub-System
ENBDM
1
LVDE LVDSE PPDC
BDM
Clock
Voltage
Regulator
Mode Regulator State
Run Full on
Wait Full on
Stop3 Standby
Stop2 Partial powerdown
Run
Stop3
Stop2
Wait
3
1
2