NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 8 LCD Module (S08LCDLPV1)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 167
9.3.5 LCD Blink Control Register (LCDBCTL)
Read: anytime
Write: anytime
7 6 5 4 3 2 1 0
R
BLINK ALT BLANK
0
BMODE BRATE2 BRATE1 BRATE0
W
Reset 0 0 0 0 0 0 0 0
Unimplemented or Reserved
Figure 9-7. LCD Blink Control Register (LCDBCTL)
Table 9-6. LCDBCTL Field Descriptions
Field Description
7
BLINK
Blink Command — Starts or stops LCD module blinking
0 Disables blinking
1 Starts blinking at blinking frequency specified by
LCD
blink rate calculation (see Equation 9-2 )
6
ALT
Alternate Display Mode — For four backplanes or less, the LCD backplane sequencer changes to output an
alternate display. ALT bit is ignored if Duty is 5 or greater.
0 Normal Display
1 Alternate display mode
5
BLANK
Blank Display Mode — Asserting this bit clears all segments in the LCD display.
0 Normal or Alternate Display
1 Blank Display Mode
3
BMODE
Blink Mode — Selects the blink mode displayed during the blink period. See Table 9-6 for more information on
how BMODE affects the LCD display.
0 Display blank during the blink period
1
Display alternate display during blink period (Ignored if duty is 5 or greater)
2:0
BRATE[2:0]
Blink-Rate Configuration — Selects frequency at which the LCD display blinks when the BLINK is asserted.
Equation 9-2 shows how BRATE[2:0] bit field is used in the
LCD
blink-rate calculation.
Equation 9-2 provides an expression for the LCD module blink rate
Eqn. 9-2
LCD module blink rate calculations are provided in Section 9.4.3.2, “Blink Frequency .”
LCD module blink rate
2
(12+ BRATE[2:0])
LCDCLK
=