M68HC16 Z SERIES
REGISTER SUMMARY
USER’S MANUAL
D-7
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
The logic state of the MM determines the value of ADDR23 for IMB module addresses.
Because ADDR[23:20] are driven to the same state as ADDR19, MM must be set to
one. If MM is cleared, IMB modules are inaccessible to the CPU16. This bit can be
written only once after reset.
IARB[3:0] — Interrupt Arbitration ID
Each module that can generate interrupts, including the SIM, has an IARB field. Each
IARB field can be assigned a value from $0 to $F. During an interrupt acknowledge
cycle, IARB permits arbitration among simultaneous interrupts of the same priority
level. The reset value of the SIM IARB field is $F, the highest priority. This prevents
SIM interrupts from being discarded during system initialization.
D.2.2 System Integration Test Register
SIMTR — System Integration Test Register
$YFFA02
Used for factory test only.
D.2.3 Clock Synthesizer Control Register
This register determines system clock operating frequency and operation during low-
power stop mode. With a slow reference frequency between 25 and 50 kHz (typically
a 32.768-kHz crystal), the clock frequency is determined by the following equation:
With a fast reference frequency between 1 and 6 MHz (typically a 4.194-MHz crystal),
the reference frequency is divided by 128 before it is passed to the PLL system. The
clock frequency is determined by the following equation:
SYNCR — Clock Synthesizer Control Register
$YFFA04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
X
Y[5:0]
EDIV
0
0
RSVD
1
NOTES:
1. Ensure that the software does not change the value of these bits. They should always be zero.
SLOCK
STSIM
STEXT
RESET:
0
0
1
1
1
1
1
1
0
0
0
0
U
0
0
0
f
sys
f
ref
4 Y
1
+
(
)
2
2W
X
+
(
)
(
)
[
]
=
f
sys
f
ref
128
----------
4 Y
1
+
(
)
2
2W
X
+
(
)
(
)
[
]
=
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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