NXP Semiconductors MC68CK16Z1, User Manual

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M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS
USER’S MANUAL A-9
Table A-10 25.17-MHz Clock Control Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
Num Characteristic Symbol Min Max Unit
1
PLL Reference Frequency Range
1
MC68HC16Z1
MC68HC16Z2
MC68HC16Z3
NOTES:
1. The base configuration of the MC68HC16Z1, MC68CK16Z1, MC68HC16Z4, and the MC68CK16Z4 requires
a 32.768 kHz crystal reference. The base configuration of the MC68CM16Z1, M68HC16Z2, and the
MC68HC16Z3 requires a 4.194 MHz crystal reference.
f
ref
20
3.2
3.2
50
5.2
5.2
kHz
MHz
MHz
2
System Frequency
2
On-Chip PLL System Frequency
Slow On-Chip PLL System Frequency
Fast On-Chip PLL System Frequency
External Clock Operation
2. All internal registers retain data at 0 Hz.
f
sys
dc
4 (f
ref
)
4 (f
ref
) /128
dc
25.17
25.17
25.17
25.17 MHz
3
PLL Lock Time
1, 7, 8, 9
Changing W or Y in SYNCR or exiting from
LPSTOP
3
Warm Start-Up
4
Cold Start-Up (fast reference option only)
5
3. Assumes that V
DDSYN
and V
DD
are stable, that an external filter is attached to the XFC pin, and that the crystal
oscillator is stable.
4. Assumes that V
DDSYN
is stable, that an external filter is attached to the XFC pin, and that the crystal oscillator
is stable, followed by V
DD
ramp-up. Lock time is measured from V
DD
at specified minimum to RESET negated.
5. Cold start is measured from V
DDSYN
and V
DD
at specified minimum to RESET negated.
t
lpll
—
—
— 20
50
75 ms
4 VCO Frequency
6
6. Internal VCO frequency (f
VCO
) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a di-
vide-by-two circuit that is not in the synthesizer feedback loop.
When X = 0, the divider is enabled, and f
sys
= f
VCO
÷
4.
When X = 1, the divider is disabled, and f
sys
= f
VCO
÷
2.
X must equal one when operating at maximum specified f
sys
.
f
VCO
— 2 (f
sys
max) MHz
5
Limp Mode Clock Frequency
SYNCR X bit = 0
SYNCR X bit = 1 f
limp
—
— f
sys
max/2
f
sys
max
MHz
6
CLKOUT Jitter
1, 7, 8, 9, 10
Short term (5
µ
s interval)
Long term (500
µ
s interval)
7. This parameter is periodically sampled rather than 100% tested.
8. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
external resistance from the XFC pin due to external leakage must be greater than 15 M
Ω
to guarantee this
specification. Filter network geometry can vary depending upon operating environment
.
9. Proper layout procedures must be followed to achieve specifications.
10. Jitter is the average deviation from the programmed frequency measured over the specified interval at maxi-
mum f
sys
. Measurements are made with the device powered by filtered supplies and clocked by a stable exter-
nal clock signal. Noise injected into the PLL circuitry via V
DDSYN
and V
SS
and variation in crystal oscillator
frequency increase the J
clk
percentage for a given interval. When jitter is a critical constraint on control system
operation, this parameter should be measured during functional testing of the final system.
J
clk
–1.0
–0.05
1.0
0.5
%
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Freescale Semiconductor, Inc.
For More Information On This Product,
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