SYSTEM INTEGRATION MODULE
M68HC16 Z SERIES
5-56
USER’S MANUAL
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. V
DD
ramp time and VCO frequency ramp time determine how long the four cy-
cles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.
is a timing diagram for power-on reset. It shows the relationships between
RESET, V
DD
, and bus signals.
Figure 5-20 Power-On Reset
5.7.8 Use of the Three-State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers
in a disabled, high-impedance state. The signal must remain asserted for approxi-
mately ten clock cycles in order for drivers to change state.
When the internal clock synthesizer is used (MODCLK held high during reset), synthe-
sizer ramp-up time affects how long the ten cycles take. Worst case is approximately
20 milliseconds from TSC assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to
high-impedance state as soon after TSC assertion as approximately ten clock pulses
have been applied to the EXTAL pin.
16 POR TIM
CLKOUT
VCO
LOCK
BUS
CYCLES
RESET
V
DD
NOTES:
1. INTERNAL START-UP TIME
2. FIRST INSTRUCTION FETCHED
2 CLOCKS
512 CLOCKS
10 CLOCKS
1
2
ADDRESS AND
CONTROL SIGNALS
THREE-STATED
BUS STATE
UNKNOWN
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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