NXP Semiconductors M5253EVBE, User Manual, Page: 44 / 56

M5253EVBE Users Manual, Rev. 1
3-4 Freescale Semiconductor
The MCF5253 processor has built in logic and up to four chip-select pins (CS[3:0]) which are used to
enable external memory and I/O devices. In addition there are SDRAS and SDCAS lines available for
controlling SDRAMs. There are registers to specify the address range, type of access and the method of
TA generation for each chip-select. These registers are programmed by the dBUG monitor to map the
external memory and I/O devices.
The M5253EVBE uses the following signals to select external peripherals:
• CS0 to enable the Flash ROM (See Section 3.1.13, “Flash ROM .”)
• SDRAS, SDCAS, and SDRAM_CS1 to enable the SDRAM (See Section 3.1.12, “SDRAM .”)
The chip select mechanism of the MCF5253 processor allows the memory mapping to be defined for the
required memory space (user/supervisor, program/data spaces).
All of the MCF5253 internal registers, configuration registers, parallel I/O port registers, UART registers
and system control registers are mapped by the MBAR registers at any 1- KByte boundary. The MBAR1
register is mapped to 0x1000_0000 and MBAR2 mapped to 0x8000_0000 by the dBUG monitor. For a
complete map of these registers, see the
MCF5253 Reference Manual .
The M5253EVBE board has 8 Mbytes of SDRAM installed. See Section 3.1.12, “SDRAM ” for a
discussion of the SDRAM on the board. The dBUG ROM monitor is programmed in one AMD
AM29LV160DB-90 flash ROM, which occupies 2 Mbytes of the address space. The first 256 Kbytes (i.e.,
the first sector) are used by the ROM monitor and the remainder is left for the user. (See
Section 3.1.13,
“Flash ROM .”)
Figure 3-1 shows the M5253EVBE memory map.
All of the unused area of the memory map is available to the user.
3.1.9 Reset Vector Mapping
After reset, the processor attempts to read the initial stack pointer and program counter values from
locations 0x0000_0000 & 0x0000_0004 (the first eight bytes of memory space). This requires the board
to have a non-volatile memory device in this range with the correct information stored in it. In some
systems, however, it is preferred to have RAM starting at address 0x0000_0000. The MCF5253 processor
Table 3-1 The M5253EVBE Memory Map
Address Range Signal and Device Memory Access Time
0x0000_0000–0x0002_0000 SDRAM space for dBug ROM monitor use Refer to manufacturer specification
0x0002_0000–0x003F_FFFF SDRAM space Refer to manufacturer specification
0x1000_0000–0x1000_03FF System Integration Module (SIM) registers Internal access
0x1000_0000–0x1000_0054 MBAR—Module base address register Refer to MCF5253RM SIM section
0x8000_0000–0x8000_0198 MBAR2—Module base address register 2 Refer to MCF5253RM SIM section
0x2000_0000–0x2000_0FFF SRAM1 Internal access (1 cycle)
0x2001_0000–0x2000_17FF SRAM0 Internal access (1 cycle)
0xFFE0_0000–0xFFFF_FFFF CS0, 2M Flash ROM 8-7-7-7