NXP Semiconductors LPC84x, User Manual

Page: 95 / 515

UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 95 of 515
NXP Semiconductors
UM11029
Chapter 8: LPC84x System configuration (SYSCON)
8.6.13 Main clock source select register
The
MAINCLKSEL
register selects the main_clock_pre_pll, which can be the FRO,
external clock, watchdog oscillator, or FRO_DIV.
Bit 0 of the MAINCLKUEN register ( Section 8.6.14 ) must be toggled from 0 to 1 for the
update to take effect.
8.6.14 Main clock source update enable register
The
MAINCLKUEN
register updates the clock source of the main clock with the new input
clock after the MAINCLKSEL register has been written to. In order for the update to take
effect, first write a zero to bit 0 of this register, then write a one.
8.6.15 System clock divider register
This register controls how the main clock is divided to provide the system clock to the
core, memories, and the perispherals. The system clock can be shut down completely by
setting the DIV field to zero.
Table 138. Main clock source select register (MAINCLKSEL, address 0x4004 8050) bit
description
Bit Symbol Value Description Reset value
1:0 SEL Clock source for main clock pre pll 0
0x0 FRO
0x1 External clock
0x2 Watchdog oscillator
0x3 FRO_DIV = FRO / 2
31:2 - - Reserved -
Table 139. Main clock source update enable register (MAINCLKUEN, address 0x4004 80 5 7 4)
bit description
Bit Symbol Value Description Reset value
0 ENA Enable main clock source update 0
0 No change
1 Update clock source
31:1 - - Reserved -
Table 140. System clock divider register (SYSAHBCLKDIV, address 0x4004 80 5 7 8) bit
description
Bit Symbol Description Reset
value
7:0 DIV System AHB clock divider values
0: System clock disabled.
1: Divide by 1.
…
255: Divide by 255. 0x01
31:8 - Reserved -