UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
385 of 515
NXP Semiconductors
UM11029
Chapter 21: LPC84x SCTimer/PWM
21.6.2 SCTimer/PWM configuration register
This register configures the overall operation of the SCTimer/PWM. Write to this register
before any other registers. Only word-writes are permitted to this register. Attempting to
write a half-word value results in a bus error.
Table 386. SCTimer/PWM configuration register (CONFIG, offset 0x000) bit description
Bit
Symbol
Value
Description
Reset
value
0
UNIFY
SCTimer/PWM operation
0
0
The SCTimer/PWM operates as two 16-bit counters named COUNTER_L and
COUNTER_H.
1
The SCTimer/PWM operates as a unified 32-bit counter.
2:1
CLKMODE
SCTimer/PWM clock mode
0
0x0
System Clock Mode. The system clock clocks the entire SCTimer/PWM module
including the counter(s) and counter prescalers.
0x1
Sampled System Clock Mode. The system clock clocks the SCTimer/PWM
module, but the counter and prescalers are only enabled to count when the
designated edge is detected on the input selected by the CKSEL field. The
minimum width of the positive and negative phases of the clock input must each
be greater than one full period of the bus/system clock. This mode is the
high-performance, sampled-clock mode.
0x2
SCTimer/PWM Input Clock Mode. The input/edge selected by the CKSEL field
clocks the SCTimer/PWM module, including the counters and prescalers, after
first being synchronized to the system clock. The minimum width of the positive
and negative phases of the clock input must each be greater than one full
period of the bus/system clock.
0x3
Asynchronous Mode. The entire SCTimer/PWM module is clocked directly by
the input/edge selected by the CKSEL field. In this mode, the SCTimer/PWM
outputs are switched synchronously to the SCTimer/PWM input clock - not the
system clock. The input clock rate must be at least half the system clock rate
and can be the same or faster than the system clock.
6:3
CKSEL
SCTimer/PWM clock select. The specific functionality of the designated
input/edge is dependent on the CLKMODE bit selection in this register.
0
0x0
Rising edges on input 0.
0x1
Falling edges on input 0.
0x2
Rising edges on input 1.
0x3
Falling edges on input 1.
0x4
Rising edges on input 2.
0x5
Falling edges on input 2.
0x6
Rising edges on input 3.
0x7
Falling edges on input 3.
0x8
Rising edges on input 4. SCT clock selected by the SYSCON SCTCLKSEL and
SCTCLKDIV registers.
0x9
Falling edges on input 4. SCT clock selected by the SYSCON SCTCLKSEL and
SCTCLKDIV registers.
7
NORELAOD_L
-
A 1 in this bit prevents the lower match registers from being reloaded from their
respective reload registers. Setting this bit eliminates the need to write to the
reload registers MATCHREL if the match values are fixed. Software can write to
set or clear this bit at any time. This bit applies to both the higher and lower
registers when the UNIFY bit is set.
0
