NXP Semiconductors LPC84x, User Manual

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User manual Rev. 1.0 — 16 June 2017 322 of 515
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Chapter 18: LPC84x SPI0/1
18.7 Functional description
18.7.1 Operating modes: clock and phase selection
SPI interfaces typically allow configuration of clock phase and polarity. These are
sometimes referred to as numbered SPI modes, as described in
Table 348 and shown in
Figure 29 . CPOL and CPHA are configured by bits in the CFG register ( Section 18.6.1 ).
Table 348. SPI mode summary
CPOL CPHA SPI
Mode
Description SCK rest
state SCK data
change edge SCK data
sample edge
0 0 0 The SPI captures serial data on the first clock transition of
the transfer (when the clock changes away from the rest
state). Data is changed on the following edge. low falling rising
0 1 1 The SPI changes serial data on the first clock transition of
the transfer (when the clock changes away from the rest
state). Data is captured on the following edge. low rising falling
1 0 2 Same as mode 0 with SCK inverted. high rising falling
1 1 3 Same as mode 1 with SCK inverted. high falling rising
Fig 29. Basic SPI operating modes
CPHA = 1
MSB LSB
MSB LSB
CPHA = 0
MISO
MOSI
SSEL
MSB LSB
MSB LSB MISO
MOSI
SSEL
Mode 0 (CPOL = 0) SCK
Mode 2 (CPOL = 1) SCK
Mode 1 (CPOL = 0) SCK
Mode 3 (CPOL = 1) SCK
Data frame
Data frame