UM11029
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
305 of 515
NXP Semiconductors
UM11029
Chapter 17: LPC84x USART0/1/2/3/4
Autobaud includes a time-out that is flagged by ABERR if no character is received at the
expected time. It is recommended that autobaud only be enabled when the USART
receiver is idle. Once enabled, either RXRDY or ABERR will be asserted at some point.
The assertion of RXRDY clears the AUTOBAUD bit automatically. The assertion of
ABERR clears the AUTOBAUD bit once the receive line goes inactive.
Autobaud has no meaning, and should not be enabled, if the USART is in synchronous
mode.
Remark:
Before using autobaud, set the BRG register to 0x0 (this is the default). This
setting allows the autobaud function to handle all baud rates.
17.7.6 RS-485 support
RS-485 support requires some form of address recognition and data direction control.
This USART has provisions for hardware address recognition (see the AUTOADDR bit in
the CFG register in
), as well as
software address recognition (see the ADDRDET bit in the CTL register in
Automatic data direction control with the RTS pin can be set up using the OESEL
,
OEPOL, and OETA bits in the CFG register (
). Data direction control can
also be implemented in software using a GPIO pin.
17.7.7 Oversampling
Typical industry standard UARTs use a 16x oversample clock to transmit and receive
asynchronous data. This is the number of BRG clocks used for one data bit. The
Oversample Select Register (OSR) allows this UART to use a 16x down to a 5x
oversample clock. There is no oversampling in synchronous modes.
Reducing the oversampling can sometimes help in getting better baud rate matching
when the baud rate is very high, or the peripheral clock is very low. For example, the
closest actual rate near 115,200 baud with a 12 MHz peripheral clock and 16x
oversampling is 107,143 baud, giving a rate error of 7%. Changing the oversampling to
15x gets the actual rate to 114,286 baud, a rate error of 0.8%. Reducing the oversampling
to 13x gets the actual rate to 115,385 baud, a rate error of only 0.16%.
There is a cost for altering the oversampling. In asynchronous modes, the UART takes
three samples of incoming data on consecutive oversample clocks, as close to the center
of a bit time as can be done. When the oversample rate is reduced, the three samples
spread out and occupy a larger proportion of a bit time. For example, with 5x
oversampling, there is one oversample clock, then three data samples taken, then one
more oversample clock before the end of the bit time. Since the oversample clock is
running asynchronously from the input data, skew of the input data relative to the
expected timing has little room for error. At 16x oversampling, there are several
oversample clocks before actual data sampling is done, making the sampling more
robust. Generally speaking, it is recommended to use the highest oversampling where the
rate error is acceptable in the system.
