NXP Semiconductors LPC822M101JDH20, User Manual, Page: 59 / 487

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User manual Rev. 1.2 — 5 October 2016 59 of 487
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Chapter 5: LPC82x System configuration (SYSCON)
To select the appropriate values for M and P, it is recommended to follow these steps:
1. Specify the input clock frequency Fclkin.
2. Calculate M to obtain the desired output frequency Fclkout with M = F
clkout
/ F
clkin
.
3. Find a value so that FCCO = 2

P

F
clkout
.
4. Verify that all frequencies and divider values conform to the limits specified in
Table 24 .
Remark: The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 100 MHz.
Table 57 shows how to configure the PLL for a 12 MHz crystal oscillator using the
SYSPLLCTRL register ( Table 24 ). The main clock is equivalent to the system clock if the
system clock divider SYSAHBCLKDIV is set to one (see Table 34 ).
Table 57. PLL configuration examples
PLL input
clock
sys_pllclkin
(Fclkin) Main clock
(Fclkout) MSEL bits
Table 24
M
divider
value PSEL bits
Table 24
P
divider
value FCCO
frequency SYSAHBCLKDIV System
clock
12 MHz 60 MHz 00100 (binary) 5 01 (binary) 2 240 MHz 2 30 MHz
12 MHz 24 MHz 00001(binary) 2 10 (binary) 4 192 MHz 1 24 MHz