UM10800
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© NXP Semiconductors N.V. 2016. All rights reserved.
User manual
Rev. 1.2 — 5 October 2016
203 of 487
NXP Semiconductors
UM10800
Chapter 13: LPC82x USART0/1/2
13.7.1.1 Fractional Rate Generator (FRG)
The Fractional Rate Generator can be used to obtain more precise baud rates when the
peripheral clock is not a good multiple of standard (or otherwise desirable) baud rates.
The FRG is typically set up to produce an integer multiple of the highest required baud
rate, or a very close approximation. The BRG is then used to obtain the actual baud rate
needed.
The FRG register controls the USART Fractional Rate Generator, which provides the
base clock for the USART. The Fractional Rate Generator creates a lower rate output
clock by suppressing selected input clocks. When not needed, the value of 0 can be set
for the FRG, which will then not divide the input clock.
The FRG output clock is defined as the inputs clock divided by 1 + (MULT / 256), where
MULT is in the range of 1 to 255. This allows producing an output clock that ranges from
the input clock divided by 1+1/256 to 1+255/256 (just more than 1 to just less than 2). Any
further division can be done specific to each USART block by the integer BRG divider
contained in each USART.
The base clock produced by the FRG cannot be perfectly symmetrical, so the FRG
distributes the output clocks as evenly as is practical. Since the USART normally uses 16x
overclocking, the jitter in the fractional rate clock in these cases tends to disappear in the
ultimate USART output.
For setting up the fractional divider use the following registers:
Table 36 “USART clock divider register (UARTCLKDIV, address 0x4004 8094) bit
description”
,
Table 40 “USART fractional generator divider value register (UARTFRGDIV,
address 0x4004 80F0) bit description”
, and
Table 41 “USART fractional generator
multiplier value register (UARTFRGMULT, address 0x4004 80F4) bit description”
.
For details see
Section 13.3.1 “Configure the USART clock and baud rate”
13.7.1.2 Baud Rate Generator (BRG)
The Baud Rate Generator (see
) is used to divide the base clock to produce
a rate 16 times the desired baud rate. Typically, standard baud rates can be generated by
integer divides of higher baud rates.
13.7.1.3 Baud rate calculations
Base clock rates are 16x for asynchronous mode and 1x for synchronous mode.
13.7.2 DMA
A DMA request is provided for each USART direction, and can be used in lieu of interrupts
for transferring data by configuring the DMA controller appropriately. The DMA controller
provides an acknowledgement signal that clears the related request when it completes
handling a that request. The transmitter DMA request is asserted when the transmitter
can accept more data. The receiver DMA request is asserted when received data is
available to be read.