NXP Semiconductors LPC822M101JDH20, User Manual, Page: 185 / 487

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User manual Rev. 1.2 — 5 October 2016 185 of 487
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Chapter 13: LPC82x USART0/1/2
For wake-up from deep-sleep and power-down modes the USART must be configured in
synchronous mode. See
Section 13.3.2 for details.
13.3.1 Configure the USART clock and baud rate
All three USARTs use a common peripheral clock (U_PCLK) and, if needed, a fractional
baud rate generator. The peripheral clock and the fractional divider for the baud rate
calculation are set up in the SYSCON block as follows (see
Figure 20 ):
1. Configure the UART clock by writing a value FRGCLKDIV > 0 in the common USART
fractional baud rate divider register. This is the divided main clock common to all
USARTs.
Table 36 “USART clock divider register (UARTCLKDIV, address 0x4004 8094) bit
description”
2. If a fractional value is needed to obtain a particular baud rate, program the fractional
divider. The fractional divider value is the fraction of MULT/DIV. The MULT and DIV
values are programmed in the FRGCTRL register. The DIV value must be
programmed with the fixed value of 256.
U_PCLK = FRGCLKDIV/(1+(MULT/DIV))
The following rules apply for MULT and DIV:
– Always set DIV to 256 by programming the FRGCTRL register with the value of
0xFF.
– Set the MULT to any value between 0 and 255.
Table 40 “USART fractional generator divider value register (UARTFRGDIV, address
0x4004 80F0) bit description”
3. In asynchronous mode: Configure the baud rate divider BRGVAL in the USARTn BRG
register. The baud rate divider divides the common USART peripheral clock by a
factor of 16 multiplied by the baud rate value to provide the
baud rate = U_PCLK/16 x BRGVAL.
Section 13.6.9 “USART Baud Rate Generator register”
4. In synchronous mode: The serial clock is Un_SCLK = U_PCLK/BRGVAL.