UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
140 of 1441
11.1 How to read this chapter
The available peripherals vary for different parts.
•
Ethernet: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.
•
USB0: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.
•
USB1: available only on LPC436x/5x/3x, LPC43S6x/S5x/S3x, and
LPC4370/LPC43S70.
•
AES: available only secure parts.
If a peripheral is not available, the corresponding bits in the CREG registers are reserved.
The following registers or register bits are implemented only on parts with on-chip flash:
•
USB0FLADJ register
•
USB1FLADJ register
•
FALSHCFGA register
•
FLASHCFGB register
•
SAMPLECTRL bit in the CREG0 register
The ARM Cortex-M0APP processor is available on all LPC43xx/LPC43Sxx parts.
The ARM Cortex-M0SUB subsystem core is only available on parts LPC4370/LPC43S70
and LPC436x/LPC43S6x.
11.2 Basic configuration
The CREG block is configured as follows:
•
See
for clocking and power control.
•
The CREG block cannot be reset by software.
UM10503
Chapter 11: LPC43xx/LPC43Sxx Configuration Registers
(CREG)
Rev. 2.1 — 10 December 2015
User manual
Table 95.
CREG clocking and power control
Base clock
Branch clock
Operating frequency
CREG
BASE_M4_CLK
CLK_M4_CREG
up to 204 MHz
