UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1188 of 1441
43.1 How to read this chapter
The SPI controller is available on all LPC43xx/LPC43Sxx parts.
43.2 Basic configuration
The SPI is configured as follows:
•
See
for clocking and power control.
•
The SPI is reset by the SPI_RST (reset # 58).
•
The SPI interrupt is connected to NVIV slot # 20 in the Cortex-M0 NVIC.
[1]
BASE_SPI_CLK
0.5 * BASE_M4_CLK (if interrupt goes to M4 or M0APP).
BASE_SPI_CLK
0.5 * BASE_PERIPH_CLK (if interrupt goes to M0SUB).
43.3 Features
•
Compliant with Serial Peripheral Interface (SPI) specification.
•
Synchronous, Serial, Full Duplex Communication.
•
SPI master or slave.
•
Maximum data bit rate of one eighth of the peripheral clock rate.
•
8 to 16 bits per transfer.
43.4 General description
SPI is a full duplex serial interface. It can handle multiple masters and slaves being
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master.
The block diagram of the SPI solution implemented in SPI interface is shown in the
.
UM10503
Chapter 43: LPC43xx/LPC43Sxx SPI
Rev. 2.1 — 10 December 2015
User manual
Table 986. SPI clocking and power control
Base clock
Branch clock
Operating
frequency
Clock to SPI; peripheral SPI
clock
CLK_SPI
up to 204 MHz
Clock to the peripheral bus
controller
BASE_PERIPH_CLK CLK_PERIPH_BUS
up
to
204 MHz
Clock to the peripheral core
controller
BASE_PERIPH_CLK BASE_PERIPH_CORE up
to
204 MHz
