UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1181 of 1441
NXP Semiconductors
UM10503
Chapter 42: LPC43xx/LPC43Sxx SSP0/1
42.7 Functional description
42.7.1 Texas Instruments synchronous serial frame format
shows the 4-wire Texas Instruments synchronous serial frame format
supported by the SSP module.
For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of the
transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to be
transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Table 985: SSP DMA Control Register (DMACR - address 0x4008 3024 (SSP0), 0x400C 5024
(SSP1)) bit description
Bit
Symbol
Description
Reset
value
0
RXDMAE
Receive DMA Enable. When this bit is set to one 1, DMA
for the receive FIFO is enabled, otherwise receive DMA is
disabled.
0
1
TXDMAE
Transmit DMA Enable. When this bit is set to one 1, DMA
for the transmit FIFO is enabled, otherwise transmit DMA
is disabled
0
31:2
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
a. Single frame transfer
b. Continuous/back-to-back frames transfer
Fig 135. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
Frames Transfer
CLK
FS
DX/DR
4 to 16 bits
MSB
LSB
CLK
FS
DX/DR
LSB
MSB
LSB
MSB
4 to 16 bits
4 to 16 bits
