NXP Semiconductors LPC43Sxx, User Manual

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User manual Rev. 2.1 — 10 December 2015 1127 of 1441
NXP Semiconductors
UM10503
Chapter 40: LPC43xx/LPC43Sxx USART0_2_3
[1] Values 0000, 0011, 010, 0111, 1000, 1001, 1010, 1011,1101, 1110,1111 are reserved.
[2] For details see Section 40.6.8 “USART Line Status Register”
[3] For details see Section 40.6.1 “USART Receiver Buffer Register”
[4] For details see Section 40.6.5 “USART Interrupt Identification Register” and Section 40.6.2 “USART
Transmitter Holding Register”
The USART THRE interrupt (IIR[3:1] = 001) is a third level interrupt and is activated when
the USART THR FIFO is empty provided certain initialization conditions have been met.
These initialization conditions are intended to give the USART THR FIFO a chance to fill
up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to THR
without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the
USART THR FIFO has held two or more characters at one time and currently, the THR is
empty. The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs
and the THRE is the highest interrupt (IIR[3:1] = 001).
40.6.6 USART FIFO Control Register
The FCR controls the operation of the USART RX and TX FIFOs.
0100 Second RX Data
Available
Rx data available or trigger level reached in
FIFO (FCR0=1) RBR
Read
[3]
or
USART
FIFO drops
below
trigger level
1100 Second Character
Time-out
indication
Minimum of one character in the RX FIFO and
no character input or removed during a time
period depending on how many characters are
in FIFO and what the trigger level is set at (3.5 to
4.5 character times).
The exact time will be:
[(word length)

7 - 2]

8 + [(trigger level -
number of characters)

8 + 1] RCLKs
RBR
Read
[3]
0010 Third THRE THRE
[2]
IIR Read
[4]
(if source of
interrupt) or
THR write
Table 931. USART Interrupt Handling
IIR[3:0]
value
[1]
Priority Interrupt
type
Interrupt source Interrupt
reset
Table 932. USART FIFO Control Register Write Only (FCR, addresses 0x4008 1008 (USART0), 0x400C 1008
(USART2), 0x400C 2008 (USART3)) bit description
Bit Symbol Value Description Reset
value
0 FIFOEN FIFO Enable. 0
0 Disabled. USART FIFOs are disabled. Must not be used in the application.
1 Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1]
access. This bit must be set for proper USART operation. Any transition on this bit
will automatically clear the USART FIFOs.