NXP Semiconductors LPC43Sxx, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 1023 of 1441
NXP Semiconductors
UM10503
Chapter 32: LPC43xx/LPC43Sxx Timer0/1/2/3
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 786. Register overview: Timer0/1/2/3 (register base addresses 0x4008 4000 (TIMER0), 0x4008 5000 (TIMER1),
0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3))
Name Access Address
offset
Description Reset
value
[1]
Reference
IR R/W 0x000 Interrupt Register. The IR can be written to clear interrupts.
The IR can be read to identify which of eight possible
interrupt sources are pending. 0 Table 787
TCR R/W 0x004 Timer Control Register. The TCR is used to control the
Timer Counter functions. The Timer Counter can be
disabled or reset through the TCR. 0 Table 788
TC R/W 0x008 Timer Counter. The 32 bit TC is incremented every PR+1
cycles of PCLK. The TC is controlled through the TCR. 0 Table 789
PR R/W 0x00C Prescale Register. When the Prescale Counter (PC) is
equal to this value, the next clock increments the TC and
clears the PC. 0 Table 790
PC R/W 0x010 Prescale Counter. The 32 bit PC is a counter which is
incremented to the value stored in PR. When the value in
PR is reached, the TC is incremented and the PC is
cleared. The PC is observable and controllable through the
bus interface.
0 Table 791
MCR R/W 0x014 Match Control Register. The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match
occurs. 0 Table 792
MR0 R/W 0x018 Match Register 0. MR0 can be enabled through the MCR
to reset the TC, stop both the TC and PC, and/or generate
an interrupt every time MR0 matches the TC. 0 Table 793
MR1 R/W 0x01C Match Register 1. See MR0 description. 0 Table 793
MR2 R/W 0x020 Match Register 2. See MR0 description. 0 Table 793
MR3 R/W 0x024 Match Register 3. See MR0 description. 0 Table 793
CCR R/W 0x028 Capture Control Register. The CCR controls which edges
of the capture inputs are used to load the Capture
Registers and whether or not an interrupt is generated
when a capture takes place. 0 Table 794
CR0 RO 0x02C Capture Register 0. CR0 is loaded with the value of TC
when there is an event on the CAPn.0 input. 0 Table 795
CR1 RO 0x030 Capture Register 1. See CR0 description. 0 Table 795
CR2 RO 0x034 Capture Register 2. See CR0 description. 0 Table 795
CR3 RO 0x038 Capture Register 3. See CR0 description. 0 Table 795
EMR R/W 0x03C External Match Register. The EMR controls the external
match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3
respectively). 0 Table 796
CTCR R/W 0x070 Count Control Register. The CTCR selects between Timer
and Counter mode, and in Counter mode selects the signal
and edge(s) for counting. 0 Table 798