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UM10316_0
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 00.06 — 17 December 2008
29 of 571
NXP Semiconductors
UM10316
Chapter 3: LPC29xx Clock Generation Unit (CGU)
3.3 Controlling the frequency dividers
The seven frequency dividers are controlled by the FDIV0..6 registers.
The frequency divider divides the incoming clock by (L/D), where L and D are both 12-bit
values, and attempts to produce a 50% duty-cycle. Each high or low phase is stretched to
last approximately D/(L*2) input-clock cycles. When D/(L*2) is an integer the duty cycle is
exactly 50%, otherwise it is an approximation.
The minimum division ratio is /2, so L should always be less than or equal to D/2. If not, or
if L is equal to 0, the input clock is passed directly to the output without being divided.
3.4 Controlling the clock output
Once a source is selected for one of the clock branches the output clock can be further
sub-divided using an output divider controlled by field IDIV in the clock-output
configuration register.
Each clock-branch output can be individually controlled to power it down and perform safe
switching between clock domains. These settings are controlled by the PD and
AUTOBLOK fields respectively.
The clock output can trigger disabling of the clock branch on a specific polarity of the
output. This is controlled via field RTX of the output-configuration register.
3.5 Reading the control settings
Each of the control registers is associated with a status register. These registers can be
used to read the configured controls of each of the CGU building blocks.
3.6 Frequency monitor
The CGU includes a frequency-monitor mechanism which measures the clock pulses of
one of the possible clock sources against the reference clock. The reference clock is the
PCR block clock CLK_PCR.
When a frequency-monitor measurement begins two counters are started. The first starts
from the specified number of reference-clock cycles (set in field RCNT) and counts down
to 0: the second counts cycles of the monitored frequency starting from 0. The
measurement is triggered by enabling it in field MEAS and stops either when the
reference clock counter reaches 0 or the measured clock counter (in field FCNT)
saturates.
The rate of the measured clock can be calculated using the formula:
Fmeas = Fcore * FCNTfinal / (RCNTinitial - RCNTfinal)
When the measurement is finished either FCNTfinal is equal to the saturated value of the
counter (FCNT is a 14-bit value) or RCNTfinal is zero.
Measurement accuracy is influenced by the ratio between the clocks. For greater
accuracy the frequency to measure should be closer to the reference clock.
