UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
211 of 362
NXP Semiconductors
UM10208
Chapter 17: LPC2800 USB Device
been "validated"; otherwise, an empty packet will be sent. Like OUT isochronous
endpoints, no interrupt is requested for IN isochronous endpoints other than the frame
interrupt.
6.4 DMA mode transfer
In DMA mode, the DMA Engine acts as a master on the AHB and transfers data between
ARM memory and the local buffer.
Endpoint 0 (the default control endpoint) receives setup packets. It is not efficient to
transfer this data to the USB RAM since the CPU has to decode embedded commands
and respond back to the host. So, setup transfers are always handled in slave mode.
For each Isochronous endpoint, one packet transfer happens every frame. Hence, DMA
transfers to or from an isochronous endpoint has to be synchronized to the frame
interrupt.
6.4.1 Data transfer between DMA engine and the USB function core
Transfer for OUT endpoints
When the endpoint has received a valid packet from the USB host, it will assert a transfer
request to the DMA engine using the flow control signals. If the DMA channel is enabled,
the corresponding DMA channel will start the data transfer between the USB core and the
DMA engine. The first data transferred to the DMA engine is a header word which tells
how many bytes are valid in the buffer. The DMA engine will transfer this word also to the
system memory. When the packet transfer is finished, the USB core will assert an
’end_of_packet’ signal to the DMA engine through the flow control ports.
In case of an ’end_of_transfer’, the DMA engine stops the data transfer permanently. It
has to be re-programmed for receiving the next packet. The DMA engine will raise an
interrupt when the transfer is finished successfully (it can also raise an interrupt when the
transfer encounters an error).
The DMA engine will also stop the data transfer when the logical DMA Channel Count
Register reaches the value zero; this is when the number of bytes written to USB memory
is equal to the initial value programmed into the Count Register.
Transfer for IN endpoints
If the DMA channel is enabled by software, it will initiate a read-transfer to the fill the DMA
memory. If the buffer for the IN endpoint is empty, the USB function core will raise a
transfer request to the corresponding DMA channel.
The DMA engine will fill its internal FIFO with the data. When the FIFO is full, it will initiate
a data transfer to the USB function core. The USB core will start filling its FIFO with the
data, and, when the FIFO is full, it will de-assert the transfer request. This will force the
DMA engine to temporarily stop the data transfer.
The packet filled in the FIFO of the USB core will be transferred to the USB host, and the
buffer will become empty again. The USB core requests for the next packet and the DMA
engine will initiate the transfer process again. This will continue until the number of bytes
transferred is equal to the value (initially) programmed in the DMA Channel Count
Register. Then the ’end_of_transfer’ is asserted. The DMA engine also generates an
