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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
586 of 808
NXP Semiconductors
UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA) controller
3. Write the first linked list item, previously written to memory, to the relevant channel in
the DMA Controller.
4. Write the channel configuration information to the channel Configuration Register and
set the Channel Enable bit. The DMA Controller then transfers the first and then
subsequent packets of data as each linked list item is loaded.
5. An interrupt can be generated at the end of each LLI depending on the Terminal
Count bit in the DMACCxControl Register. If this bit is set an interrupt is generated at
the end of the relevant LLI. The interrupt request must then be serviced and the
relevant bit in the DMACIntTCClear Register must be set to clear the interrupt.
6.5.1.2
Example of scatter/gather DMA
for an example of an LLI. A rectangle of memory has to be transferred
to a peripheral. The addresses of each line of data are given, in hexadecimal, at the
left-hand side of the figure. The LLIs describing the transfer are to be stored contiguously
from address 0x20000.
The first LLI, stored at 0x20000, defines the first block of data to be transferred, which is
the data stored between addresses 0x0A200 and 0x0AE00:
•
Source start address 0x0A200.
•
Destination address set to the destination peripheral address.
•
Transfer width, word (32-bit).
•
Transfer size, 3072 bytes (0XC00).
•
Source and destination burst sizes, 16 transfers.
•
Next LLI address, 0x20010.
The second LLI, stored at 0x20010, describes the next block of data to be transferred:
•
Source start address 0x0B200.
•
Destination address set to the destination peripheral address.
•
Transfer width, word (32-bit).
•
Transfer size, 3072 bytes (0xC00).
Fig 133. LLI example
0x--200
0x–E00
0x0A---
0x0B---
0x0C---
0x0D---
0x0E---
0x0F---
0x10---
0x11---