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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
270 of 808
1.
Basic configuration
The UART0/2/3 peripherals are configured using the following registers:
1. Power: In the PCONP register (
), set bits PCUART0/2/3.
Remark:
On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled
(PCUART2/3 = 0).
2. Peripheral clock: In the PCLKSEL0 register (
), select PCLK_UART0; in the
PCLKSEL1 register (
), select PCLK_UART2/3.
3. Baud rate: In register U0/2/3LCR (
), set bit DLAB =1. This enables
access to registers DLL (
) and DLM (
) for setting the baud
rate. Also, if needed, set the fractional baud rate in the fractional divider register
(
4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR (
enable FIFO.
5. Pins: Select UART pins through the PINSEL registers and pin modes through the
PINMODE registers (
Remark:
UART receive pins should not have pull-down resistors enabled.
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR
(
). This enables access to U0/2/3IER (
). Interrupts are
enabled in the NVIC using the appropriate Interrupt Set Enable register.
7. DMA: UART0/2/3 transmit and receive functions can operate with the GPDMA
controller (see
2.
Features
•
16 byte Receive and Transmit FIFOs.
•
Register locations conform to ‘550 industry standard.
•
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
•
Built-in baud rate generator.
•
Fractional divider for baud rate control, autobaud capabilities and mechanism that
enables software flow control implementation.
•
DMA support for both transmit and receive.
•
IrDA mode to support infrared communication.
3.
Pin description
UM10360
Chapter 14: LPC17xx UART0/2/3
Rev. 00.06 — 5 June 2009
User manual
Table 247: UARTn Pin description
Pin
Type
Description
RXD0, RXD2, RXD3
Input
Serial Input.
Serial receive data.
TXD0, TXD2, TXD3
Output
Serial Output.
Serial transmit data.